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PLD SPLD GAL CPLD FPGA
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help with fpga clock?
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Topic: help with fpga clock? (Read 263 times)
Bob_Skalze
Newbie
Posts: 3
help with fpga clock?
«
on:
June 19, 2011, 12:54:13 PM »
i'm using a spartan 3an starter kit. the board comes with a 50 MHz clock but i want a 40 MHz clock. so
i changed the constraints and the program generated this line:
NET "clock" TNM_NET = clock;
TIMESPEC TS_clock = PERIOD "clock" 25 ns HIGH 50%;
no errors occur but when i run this program on the board it does nothing however if i use the 50MHz clock it works fine. What could be wrong?
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doublee
Newbie
Posts: 4
Re: help with fpga clock?
«
Reply #1 on:
June 19, 2011, 12:58:12 PM »
Defining a constraint only tells the program to route the gates in order to meet this timing but won't actually change the clock frequency. You have to instantiate a DCM to convert your 50Mhz clock to a 40Mhz clock. The Spartan 3 users guide describes the DCM in detail. You'll have to come up with a suitable multiply/divide ratio to get the proper frequency.
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