'Verilog vs VHDL' for FPGA programming?

VHDL provides more detail in the assignment and application of individual cells and signals within the FPGA but is more difficult to use and requires a much better understanding of the FPGA.

Verilog is an easier, higher level language (using conscripts that are similar to 'C') that compiles down to the individual cell assignment and applications - easier, but often it is not as efficient in use of the available cells, nor does it necessarily generate the fastest running implementation from the components available in the FPGA.

It's somewhat like comparing Assembly language (as VHDL) to C (as Verilog).