7 Segment display help. ;[?

I am given task:

design an octal-to-7-segment common cathode decoder for digits 0 to 5 only using the least possible number of basic gates (i.e. an optimum design). The 7-segment will only need to display from octal digits 0 to 5, ignore other numbers Your solutions must show all the design steps taken, i.e. a description of the task, requirements definition, design approaches such as truth-table(s), simplification using K-maps or Boolean theorems, and the implementation (circuit diagrams) using standard logic symbols.

I have come out with the truth table. But i'm clueless about the basic gates needed, simplification using K-maps or Boolean theorem,

3 switches name A, B, C.
so when the switches are:
* A=off/0 B=off/0 C=off/0 *, the display will be 0
* A=off/0 B=off/0 C=on/1 *, the display will be 1
* A=off/0 B=on/1 C=off/0 *, the display will be 2
* A=off/0 B=on/1 C=on/1 *, the display will be 3
* A=on/1 B=off/0 C=off/0 *, the display will be 4
* A=on/1 B=off/0 C=on/1 *, the display will be 5

Would REALLY REALLY appreciate if anyone can help.
Hi, thanks for the reply. I am using NI multisim to design the circuit but it does have "74185 Binary to BCD". I tried but i can't get the correct out come

http://www.flickr.com/photos/64214999@N05/5847860619/sizes/l/in/photostream/

Thank you
Hey Misanthrope,

Thanks for the help. Yup you right, i have to use basic gates.


I did the truth table:

ABC: 000                a: 1 b: 1 c: 1 d: 1 e: 1 f: 1 g:0
ABC: 001                a: 0 b: 1 c: 1 d: 0 e: 0 f: 0 g:0
ABC: 010                a: 1 b: 1 c: 0 d: 1 e: 1 f: 0 g:1
ABC: 011                a: 1 b: 1 c: 1 d: 1 e: 0 f: 0 g:1
ABC: 100                a: 0 b: 1 c: 1 d: 0 e: 0 f: 1 g:1
ABC: 101                a: 1 b: 0 c: 1 d: 1 e: 0 f: 1 g:1
ABC: 110                a: 1 b: 0 c: 1 d: 1 e: 1 f: 1 g:1
ABC: 111                a: 1 b: 1 c: 1 d: 0 e: 0 f: 0 g:0

But how do i start the K-map for this? Like an eg.
 "then write down the Karnaugh maps for each of the 7-segments inputs (A,B,C...) and find the simplified Boolean expression."

Thanks Alot.

First you have to write down the full truth table, the one you wrote is incomplete...you have to write the logical states for the 7-segments too (A,B,C,D,E,F,G)
for example:
a=0 b=0 c=0 , the display will be 0, so the logic states for the 7-segments inputs would be: A=1 B=1 C=1 D=1 E=1 F=1 G=0

a=0 b=0 c=1 , the display will be 1, so the logic states for the 7-segments inputs would be:A=0 B=1 C=1 D=0 E=0 F=0 G=0

and so forth...

then write down the Karnaugh maps for each of the 7-segments inputs (A,B,C...) and find the simplified Boolean expression.

after this just implement each input ,depending on Boolean expressions you've found, using the basic logical gates.

This is not a complete solution, just the steps
btw, using IC's here won't be right, since you're not using the basic gates and even not designing the decoder\circuit.